This invention relates to a semiconductor memory device and more particularly to a dynamic random access memory (hereinafter referred to as a "dynamic RAM") having an operating mode in which data of a plurality of bits can be read out or written in serially.
The address multiplex system, in which address signals are applied twice separately as an address designation system, has been employed in semiconductor memory devices with a large memory capacity, such as in 64K bit (65,536 bits) dynamic RAMs, in order to reduce the number of pins on the package holding the memory device. When this address multiplex system is used for a 64K bit dynamic RAM, the number of pins on the package may be 16. In other words, the 64K bit dynamic RAM is placed in a 16-pin package.
The function of each pin is standarized, as shown in FIG. 4, when packaging a 64K bit dynamic RAM in a 16-pin package. In other words, 16-bit address signals are applied twice separately to pins 5-7 and to pins 9-13. Pin 1 is generally used for refresh (although in FIG. 4 it is shown for the address bit A.sub.8 used for 256K bit memories as will be explained hereafter), pins 2 and 14 are used as data input and output pins, and pin 3 as a write enable signal (WE) input pin. Pins 4 and 15 are used as input pins for a row address strobe signal RAS (hereinafter referred to as "RAS signal") and a column address strobe signal CAS (hereinafter referred to as "CAS signal"), and pins 8 and 16 as power pins.
256K bit (=262,144 bits) dynamic RAMs have been developed extensively in recent years. The number of address signals is greater in a 256K bit dynamic RAM than in a 64K bit dynamic RAM. In order to construct a 256K bit dynamic RAM while securing an input pin for refresh control signals, therefore, the design concept of the conventional 64K bit RAM must be changed to either increase the number of pins or detect the refresh timing from the relationship of the timings of the RAS and CAS signals, thereby making it possible to use pin 1 of the 16-pin package as an input pin for an address signal A.sub.8 as shown in FIG. 4. However, compatibility between the 64K bit dynamic RAM and the 256K bit dynamic RAM is lost in the former case. Although the latter case is compatible with 64K bit RAMs (because only 16 pins are necessary), it does prevent the normal use of the pin (i.e. pin 1) typically designated for the refresh operation. Also, this arrangement is somewhat slower in addressing speed than is sometimes desired.
In order to develop a dynamic RAM having a greater memory capacity such as a 1M bit (=1,024,000 bits) dynamic RAM, an increase in the number of pins is inevitable unless the design concept itself can be changed.